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Title:
GATE ARRAY INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH01256221
Kind Code:
A
Abstract:

PURPOSE: To fix the logic value of an input terminal not in use without using a wiring area and a cell by connecting the input terminal not in use among input terminals to an emitter (source) of a transistor(TR) element.

CONSTITUTION: The base and emitter of a TR2 are connected by a wire 1 by fixing a logic value of the input terminal 1 not in use to level '1'. Thus, the level of the input terminal 11 is always logical '1'. That is, since the logic value of the input terminal not in use is fixed by using only a wire of a short- distance as the connection of the base and emitter of the TR, it is not required to use the wire area or the other cell for the constitution of the circuit. Thus, the chip size is reduced.


Inventors:
KAKIMOTO MASAO
Application Number:
JP8461988A
Publication Date:
October 12, 1989
Filing Date:
April 06, 1988
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L27/04; H01L21/82; H01L21/822; H01L27/118; H03K19/086; H03K19/094; H03K19/0948; H03K19/173; (IPC1-7): H01L21/82; H01L27/04; H03K19/086; H03K19/094; H03K19/173
Attorney, Agent or Firm:
Yanagi Shin Kawai



 
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