PURPOSE: To efficiently use a cell and to realize a large-scale integration of a chip by a method wherein a wiring part for highest-potential clamping use and a wiring part for lowest-potential clamping use are connected respectively to pads for power supply use via high-impedance elements.

CONSTITUTION: A high-potential-side power-supply wiring part 7 which is formed of a low-resistance wiring material (e.g. Al) and which is arranged so as to pierce fundamental-cell row regions 2 is connected to a pad 5 for highest- potential power-supply use. In addition, wiring parts 9, for highest-potential clamping use, which pierce the unit gate-cell row regions 2 and which are arranged in parallel with the high-potential-side power-supply wiring part 7 are connected via diffusion resistance elements 8. In the same manner, low-potential- side power-supply wiring parts 10 which are arranged so as to pierce the fundamental-cell row regions 2 are connected to a lowest-potential power-supply pad 6. In addition, wiring parts 11, for lowest-potential clamping use, which pierce the fundamental unit cell row regions 2 and which are formed in parallel with the low-potential-side power-supply wiring parts 10 are connected via the diffusion resistance elements 8.