PURPOSE: To easily judge whether a wafer process has been finished satisfactorily or not when a defect is caused by a method wherein a pattern size for chip-monitor mounting use is formed between a pattern region for input/output buffer circuit mounting use and a pattern region for internal logic circuit mounting use.

CONSTITUTION: A circuit-constituent element and a wiring part which correspond to a customer's logic circuit are arranged and wired by using a computer in a pattern region 1 for input/output buffer circuit mounting use and a pattern region 2 for internal logic circuit mounting use. On the other hand, a transistor pattern on the pattern region 2 for internal logic circuit mounting use, i.e., the pattern identical to a basic cell, is arranged in a pattern region 3 for chip- monitor mounting use; a logic circuit which can analyze a defect easily is assembled by a metal wiring process. Thereby, it is possible to monitor how a wafer process on the pattern region 2 for internal logic circuit mounting use has been finished; it is possible to easily analyze a defect of a product.