To provide a process for manufacturing a high voltage FET (field-effect transistor).
This process for manufacturing the high voltage FET comprises the steps of: forming a first and second trenches by etching a first and second dielectric regions, which is made by passing through a first and second openings of a mask layer with a substantially isotropic method, wherein the first and second dielectric regions are positioned on respective opposite sides of a mesa of semiconductor material, and the mesa has the first and second side walls respectively adjacent to the first and second dielectric regions; etching the first and second regions in the first and second trenches by a substantially isotropic method, and then exposing the first and second side walls of the mesa; and forming gate oxide on the first and second side walls of the mesa. This summary of the invention disclosed is offered to searchers or other viewers as to be able to search quickly.
| JP2663668 | [Title of Invention] Structure of Power MOSFET |
| WO/2014/163603 | PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE |
| JPH03209865 | INVERTER CIRCUIT |
| JP2003204064A | 2003-07-18 | |||
| JPH02252264A | 1990-10-11 | |||
| JP2002313773A | 2002-10-25 | |||
| JP2005534978A | 2005-11-17 |
Fumiaki Otsuka
Takaki Nishijima
Hiroyuki Suda