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Patent Searching and Data


Title:
GATE-INSULATED BIPOLAR TRANSISTOR
Document Type and Number:
Japanese Patent JPH01238171
Kind Code:
A
Abstract:

PURPOSE: To prevent a latching effect without a diffusion potential between a source layer and a channel layer being exceeded by the potential change under a source layer, by collecting carrier to be injected from a drain region by one conductivity type layer in the drain region under the channel layer.

CONSTITUTION: The same conductivity type P+ type collector layer 32 as that of a channel forming layer is formed with substantially the same width in the N- type layer 2 of a drain region under the P-type layer 3 of a channel layer, and connected by a P+ type layer 31 to the layer 3 and a source electrode. Part of carrier (hole) 11 injected from a P+ type layer 1 to a drain region 2 is collected to the layer 32 of a collector layer, and the number of holes arriving at the layer 3 of an N+ type layer 4 is reduced. An important point to design an IGBT is of an interval W of the region 2 between the layers 32 for collecting the carrier. If the interval is excessively narrow, resistance is increased against the carrier (electrons) injected from a source layer 4 designated by a solid line 12, thereby causing a voltage drop between a source electrode 7 and a drain electrode 8 to increase.


Inventors:
MIURA SHUNJI
Application Number:
JP6542488A
Publication Date:
September 22, 1989
Filing Date:
March 18, 1988
Export Citation:
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Assignee:
FUJI ELECTRIC CO LTD
International Classes:
H01L29/68; H01L29/10; H01L29/739; H01L29/78; (IPC1-7): H01L29/68; H01L29/78
Attorney, Agent or Firm:
Iwao Yamaguchi