Title:
GENERAL-PURPOSE CHARGE MODE ANALOG ARITHMETIC CIRCUIT
Document Type and Number:
Japanese Patent JP2563090
Kind Code:
B2
Abstract:
PURPOSE: To perform the arithmetic operation of a new concept unlike before that moves an arithmetic function without moving data by associatively controlling plural adjacent charge transfer elements on a circuit and performing a necessary arithmetic function for analog charge signals on the circuit.
CONSTITUTION: Storage gates Sij are arranged at grating points of a square grating, and control gates Cij and C'ij connect adjacent storage gates along the grating. Here, the storage gates and control gates function to form a potential well in a semiconductor substrate below them according to an applied potential, and the control gates function to connect and separate the potential wells of two adjacent storage gates. The arithmetic unit can perform various arithmetic operations such as DA conversion, 2-quadrant multiplication, 4-quadrant multiplication, AD conversion, floating-point division, block addition, and the parallel rearrangement of an inverter, a data transfer line, a delay line, and spatial data according to the control mode.
Inventors:
NAGAZUMI YASUO
Application Number:
JP29053794A
Publication Date:
December 11, 1996
Filing Date:
October 31, 1994
Export Citation:
Assignee:
JII DEII ESU KK
NAGAZUMI YASUO
NAGAZUMI YASUO
International Classes:
G06G7/06; G06J1/00; H03K17/00; G06G7/12; H03M1/02; H03M1/66; (IPC1-7): G06G7/12; H03M1/02; H03M1/66
Attorney, Agent or Firm:
Nobuyuki Iida