To provide a generator for generating a pulse width modulation(PWM) signal which can vary the duty cycle of the PWM signal with a good responsibility without disturbing the period of the PWM signal.

Based on an ON-time data TON calculated every predetermined time by a CPU and stored in a RAM which represents the count value corresponding to a high-level time per one cycle (CYCL) of a PWM signal, a circuit for generating and outputting the PWM signal for driving an electrical load clocks repeatedly by a down-counter the half-period time of the PWM signal, and whenever the count value CNT of the down-counter becomes zero, the circuit inverts a flag PFLG1 and reads the ON-time data TON from the RAM. Then, when during the term of the flag PFLG1 being high the foregoing count value CNT becomes the half value of the ON-time data TON, the circuit makes high the PWM signal. Further, when during the term of the flag PFLG1 being low the foregoing count value CNT becomes the half value of the value obtained by subtracting the ON-time data TON from the value corresponding to the one cycle time of the PWM signal, the circuit makes low the PWM signal.