Title:
MANUFACTURE OF SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3123222
Kind Code:
B2
Abstract:
PURPOSE: To achieve that an SOG residue is not left on a first-layer bonding pad and to reduce an excessive overetching operation after that regarding the formation method of bonding pads in a multilayer process.
CONSTITUTION: In the manufacture the following are installed: a process wherein a first bonding pad 2 which is provided with protruding parts and recessed parts are formed on a substrate film 1 which has been applied onto a semiconductor substrate; a process wherein a first insulating film 3 is applied onto the substrate film 1 so as to cover the first-layer bonding pad 2; a process wherein a spin-on-glass(SOG) film 4 is applied onto the first insulating film 3; and a process wherein the SOG film is etched back and the SOG film 4 at least on the protruding parts in the first-layer bonding pad 2 is removed. Then, the manufacture is constituted so as to form a second-layer bonding pad 6 on the whole surface of contact holes by means of the following: a process wherein a second insulating film 5 is applied onto the whole surface of the semiconductor substrate; and a process wherein the contact holes are made in the second insulating film 5 on the first-layer bonding pad 2.
Inventors:
Takahiko Mizutani
Application Number:
JP15102992A
Publication Date:
January 09, 2001
Filing Date:
June 11, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/316; H01L21/60; (IPC1-7): H01L21/60
Domestic Patent References:
| JP6377126A | ||||
| JP191439A | ||||
| JP226039A |
Attorney, Agent or Firm:
Teiichi Igeta