Title:
GLITCH NOISE ELIMINATION CIRCUIT
Document Type and Number:
Japanese Patent JPH04287512
Kind Code:
A
Abstract:
PURPOSE: To eliminate undesired glitch noise whose width is a delay time (t) of a delay circuit or below completely without deterioration in the waveform.
CONSTITUTION: The circuit is provided with a delay circuit 1 delaying an input signal by a prescribed time, a NAND circuit 2 and an OR circuit 3 receiving an output signal of the delay circuit and the input signal and an S-R flip-flop 4 receiving an output signal of the NAND circuit 2 as its set signal and receiving an output signal of the OR circuit 3 as its reset signal.
Inventors:
SAKAKIBARA JUNICHI
Application Number:
JP5190991A
Publication Date:
October 13, 1992
Filing Date:
March 18, 1991
Export Citation:
Assignee:
NEC CORP
International Classes:
H03K5/00; (IPC1-7): H03K5/00
Attorney, Agent or Firm:
Uchihara Shin