Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3151904
Kind Code:
B2
Abstract:
PURPOSE: To prevent potential fluctuation of a constant voltage circuit due to noise, by applying a constant voltage outputted from a second constant voltage circuit to a resistance island of a first constant voltage circuit, as a bias voltage.
CONSTITUTION: A constant voltage Vref' outputted from a constant voltage circuit 27 is applied, as a bias voltage, to a resistance island 30 formed by resistors constituting a constant voltage circuit 27. The constant voltage Vref' outputted from the constant voltage circuit 27 is applied, as a bias voltage, also to a resistance island 16 formed by resistors constituting a constant voltage circuit 26. Thereby noise is not superposed on the constant voltage Vref' outputted from the constant voltage circuit 27, when the noise is generated in a power supply voltage VCC, because a VCC power supply line 1 is not connected with the resistance island 30. Further, since a constant voltage supply line 37 is not necessary to be formed long, noise from the VCC power supply line 1 and a signal line is not superposed on the constant voltage supply line 37.
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Inventors:
Masaya Tamamura
Shinji Emori
Shinji Emori
Application Number:
JP1551592A
Publication Date:
April 03, 2001
Filing Date:
January 30, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
G05F3/26; H01L21/822; H01L27/04; (IPC1-7): H01L27/04; G05F3/26; H01L21/822
Domestic Patent References:
| JP61283142A | ||||
| JP62274764A | ||||
| JP5849449U |
Attorney, Agent or Firm:
Tetsuo Hirado