To provide a graphics controller for high-speed transmission of memory read command.

This memory controller chip includes a logic circuit connected to a first memory, this logic circuit responds to the first command issued from a CPU by determining the condition whether the first command is a memory reading command is true; if the condition is true, the logic circuit, while making hold the memory controller chip the first command to the first memory, the execution of the first command is made to begin; but if the condition is false, the logic circuit make the memory controller chip check whether preparation of performing the first command is true; and if the memory controller chip is not ready to carry out the first command, the logic circuit, while making the memory controller chip continue to check, transmits a signal to the CPU that the second command from the CPU is ready to receive.