Title:
RAM SCANNER
Document Type and Number:
Japanese Patent JP3190748
Kind Code:
B2
Abstract:
PURPOSE: To reduce the load of a CPU and to shorten processing time by eliminating the occupation of the CPU for comparison of priority to decide the priority of transmitting messages in a RAM or the search of the position of the received message inside the RAM.
CONSTITUTION: With a counter as an address, the message of a RAM 12 is read through a dedicated bus 17 and latched to a latch circuit 21. Then, the ID is compared with that of a message already latched in a latch circuit 23. When the priority of the message in the latch circuit 21 is higher in this case, a BORO signal is generated, the data of the latch circuit 21 are latched to the latch circuit 23, and an address outputted from a latch circuit 26 is latched to a register 24. Afterwards, a counter 25 repeats counting just for the number of messages written in the RAM 12, the ID of the message judged the higher transmission priority as the subtracted result is latched to the latch circuit 23, and the address of that message is latched to the register 24.
Inventors:
Yasuhiro Nakamura
Application Number:
JP30991692A
Publication Date:
July 23, 2001
Filing Date:
November 19, 1992
Export Citation:
Assignee:
NC Microsystem Co., Ltd.
International Classes:
G06F12/00; G06F13/18; G06F17/30; (IPC1-7): G06F12/00; G06F13/18
Domestic Patent References:
| JPS62224823A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)