Title:
POWER CONSUMPTION LOWERING CIRCUIT FOR MICROPROCESSOR
Document Type and Number:
Japanese Patent JPH0651861
Kind Code:
A
Abstract:
PURPOSE: To sufficiently lower power consumption in a standby state by shortening the time required for that a microprocessor restarts the operation from the standby state.
CONSTITUTION: When an incorporated register 20 is accessed from the microprocessor, corresponding to a wait signal, a clock control circuit 12 turns the microprocessor to a wait state and waits an output address and when data instructing clock stop are written in the register 20, a switch 16 is opened while the microprocessor 10 is set in the wait state. Afterwards, when the command signal of operation restart is supplied, the wait state of the microprocessor is canceled, the switch 16 is closed, and the supply of clocks to the microprocessor 10 is restarted.
Inventors:
NAKAMURA TAKAHARU
KAWABATA KAZUO
OBUCHI KAZUCHIKA
ITO KENICHI
KAWABATA KAZUO
OBUCHI KAZUCHIKA
ITO KENICHI
Application Number:
JP20679492A
Publication Date:
February 25, 1994
Filing Date:
August 03, 1992
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
G06F1/32; G06F1/04; (IPC1-7): G06F1/04; G06F1/32
Attorney, Agent or Firm:
Tadahiko Ito
Next Patent: POWER CONTROLLER