PURPOSE: To improve throughput and reliability.
CONSTITUTION: Address mask parts 11A and 11B mask the designated bits of addresses on address buses 101A and 101B with address mask patterns set by processors 16A and 16B and output them to address comparison parts 12A and 12B. The address comparison parts 12A and 12B compare the addresses masked by the address mask parts 11A and 11B, detect the coincidence/non- coincidence of those addresses and output the result to access permission judge parts 13A and 13B. The access permission judge parts 13A and 13B judge the permission/non-permission of access to shared memories 14A and 14B from internal occupation signals 104B and 104A outputted from the other processors 16B and 16A, memory occupation signals 106B and 106A, the compared result of the address comparison parts 12A and 12B, and access instruction kinds 108A and 108B from the processors 16A and 16B.
WO/2023/171474 | MEMORY CONTROLLER AND MEMORY CONTROL METHOD |
WO1999024994 | ELECTRONIC BOOK SYSTEM |
JP3289605 | HARDWARE RESOURCE MANAGEMENT MODULE MAKING COMMON SYSTEM |
JPS5417643A | 1979-02-09 | |||
JPH01251156A | 1989-10-06 | |||
JPH03160551A | 1991-07-10 |