PURPOSE: To transmit a signal without hazard as an output of a final stage by inputting an external input signal to a 1st counter means in flip-flop operation and sending an output resulting from shifting a tail edge of an input signal for every input of a clock signal.

CONSTITUTION: In order to segment an output signal (c) in 1-bit width formed by using a 1st clock (a) at a 2nd clock (f) slower than the 1st clock (a) when the output signal (c) is logical 1, a timing (1) of the said output signal (c) is extended up to a time to be segmented by the 2nd clock. Thus, a 1st OR circuit 15 is provided between 1st and 2nd FFs 11, 12, and a 2nd OR circuit 16 is provided between 2nd and 3rd FFs 12, 13, and the output signal (d) of the 2nd OR circuit 16 is segmented by the 3rd FF 13 to form an output signal (e) in which its level is logical 1 for three-clock width and the rising (5) of the 2nd clock is surely latched while the output signal (e) is logical 1 to prevent malfunction.