To inexpensively provide an HDLC control circuit realizing support of an HDLC bit synchronous system in a network terminal by using an existing LSI (gate array) performing a two layer processing for supporting an HDLC octet synchronous system.
Since the development of an FPGA is more inexpensive than that of a gate array in general, the FPGA converting the HDLC synchronous system without changing the LSI (gate array) for performing the two layer processing is developed and it is connected to the line side of the LSI performing the two layer processing. The FPGA has a function for converting an octet synchronous HDLC frame into a bit synchronous HDLC frame in transmission and converting the bit synchronous HDLC frame into the octet synchronous HDLC frame in reception.
TANAKA MASANOBU
ANZAI ATSUSHI
HITACHI PROCESS COMPUTER ENG
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