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Title:
HEAT-TREATMENT METHOD
Document Type and Number:
Japanese Patent JP3474261
Kind Code:
B2
Abstract:

PURPOSE: To prevent a slip from being generated when a wafer as an object to be treated is heat-treated by a method wherein the wafer is heat-treated at a temperature- rise pattern whose temperature-rise speed grade is smaller than that of a limit temperature-rise speed pattern which can prevent the generation of the slip of the object, to be treated, at a predetermined treatment temperature.
CONSTITUTION: Many semiconductor wafers W are held by a ladder boat 6, the arrangement pitch of the wafers W is set, e.g. at 3/16 inch, and they are carried into a reaction tube 2. Then, the temperature at the inside of the reaction tube 2 is raised at high speed, e.g. at 34°C/min, until a heat-treatment region inside the reaction tube 2 becomes a temperature of about 900°C. Then, after the temperature of the heat-treatment region inside the reaction tube 2 has reached 900°C, the temperature is raised stepwise at low speed, e.g. at about 10°C/min, up to 980°C and, in addition, at about 5°C/min up to 1100°C. The temperature-rise speed is set on the basis of a result by observing the existence of the generation of a slip while various temperature-rise speed patterns are changed at every arrangement pitch of the wafers W. Thereby, it is possible to prevent the slip from being generated while the wafers are being treated at a high throughput.


Inventors:
Junichi Kobayashi
Eiichiro Takanabe
Application Number:
JP12812794A
Publication Date:
December 08, 2003
Filing Date:
May 17, 1994
Export Citation:
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Assignee:
東京エレクトロン株式会社
International Classes:
C23C16/46; C30B31/12; C30B31/14; H01L21/22; F27B5/18; H01L21/316; H01L21/324; (IPC1-7): H01L21/22; H01L21/316; H01L21/324
Domestic Patent References:
JP56894A
JP437028A
JP63128623A
Attorney, Agent or Firm:
Toshio Inoue