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Title:
HETERO JUNCTION BIPOLAR SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JPS6050957
Kind Code:
A
Abstract:

PURPOSE: To reduce the base resistance and the emitter junction area of a semiconductor device by laminating a collector, a base, and an emitter of the prescribed energy band width Eg on a semiconductor substrate, cutting-out to the base layer with electrodes as masks, filling the cut-out with the same conductive type layer as the base, and attaching a base electrode to the surface.

CONSTITUTION: An N+ type buffer 12, an N type collector 13, a P+ type base 14, an N type Al0.3Ga0.7As emitter 15, and an N+ type cap layer 16 are laminated on an N+ type GaAs substrate 1 by a molecule beam epitaxial method, a Ge film 17 and a W5Si3 film 18 are laminated, an emitter electrode 20 is formed by a resist mask 19, and etched to form a cutout 21, thereby exposing the base 14. A P+ type Al0.3Ga0.7As film 22 is selectively grown at the cutout, an Au film 23, a Zn film 24 and an Au film 23' are superposed, an AuGe film 26 and an Au film 27 are superposed on the back surface of the substrate, alloyed to form collector electrodes 28, the metal layer of the surface is patterned, alloyed to form a base electrode 25 to complete this. The layer 15 needs Eg wider than the layer 14. According to this construction, ultrafine pattern can be formed accurately, thereby reducing the semiconductor device with good reproducibility.


Inventors:
OOSHIMA TOSHIO
YOKOYAMA NAOKI
Application Number:
JP15802383A
Publication Date:
March 22, 1985
Filing Date:
August 31, 1983
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L29/205; H01L21/331; H01L29/72; H01L29/73; H01L29/737; (IPC1-7): H01L29/20
Domestic Patent References:
JPS5185677A1976-07-27
Attorney, Agent or Firm:
Shoji Kashiwaya



 
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