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Patent Searching and Data


Title:
HETERO JUNCTION BIPOLAR TRANSISTOR
Document Type and Number:
Japanese Patent JPS63157468
Kind Code:
A
Abstract:

PURPOSE: To reduce the effective base resistance during high speed operation bringing the high speed performances into full play by a method wherein an insulator layer is partly laid between base contact parts.

CONSTITUTION: A collector layer comprising N+ and N type GaAs 2, 3, a P type GaAs inner base 4 and a P type AlGaAs outer base 6 as well as N type AlGaAs 8∼10 and an N+ type GaAs emitter 11 are laminated on a semiconductor GaAs substrate 1; and an insulator layer is partly buried in the contact part between the base electrode 16 and the outer base 6. Through these procedures, when an insulator is laid between the half parts of contact part, the capacity C between electrode and base layer is halved in the insulator layer part; the contact resistance R is doubled if whole body is in ohmic contact; the base input impedance parallels 2R and ωC when actuated in the frequency of ω and the effective value thereof becomes smaller than the contact resistance R without fail if insulator is not provided so that the impedance may be substantially reduced to make the high speed operation feasible.


Inventors:
AKAGI JUNKO
KATO RIICHI
MORITSUKA KOHEI
Application Number:
JP30366986A
Publication Date:
June 30, 1988
Filing Date:
December 22, 1986
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H01L29/73; H01L21/331; H01L29/205; H01L29/72; H01L29/737; (IPC1-7): H01L29/205; H01L29/72
Attorney, Agent or Firm:
Takehiko Suzue