Title:
HETERODYNE RECEIVER
Document Type and Number:
Japanese Patent JP2010147902
Kind Code:
A
Abstract:
To reduce the load on an image suppression rate compensating circuit.
A heterodyne receiver includes a power detector 13 for measuring the power value of a desired signal; a power detector 14 for measuring the power value of an image signal; a compensation circuit 12 for compensating for an image suppression rate; and a control section 15 which compares the power value of the desired signal with the power value of the image signal and controls the compensation circuit 12, on the basis of the result of the comparison.
COPYRIGHT: (C)2010,JPO&INPIT
Inventors:
KITAYABU TORU
Application Number:
JP2008324139A
Publication Date:
July 01, 2010
Filing Date:
December 19, 2008
Export Citation:
Assignee:
KDDI CORP
International Classes:
H04B1/26; H04L27/00
Attorney, Agent or Firm:
Sumio Tanai
Masatake Shiga
Yoshifumi Saeki
Naoki Ofusa
Masatake Shiga
Yoshifumi Saeki
Naoki Ofusa