Title:
HETEROJUNCTION TRANSISTOR
Document Type and Number:
Japanese Patent JPH05129321
Kind Code:
A
Abstract:
PURPOSE: To obtain a transistor which can realize a heterojunction in an emitter even when a polycrystalline silicon carbide layer at the uppermost layer is used as an emitter layer and a collector layer.
CONSTITUTION: A β-type single-crystal silicon carbide layer 22 is formed on a single-crystal silicon substrate 20 (A). A polycrystalline silicon layer 24 is formed on it (B). In addition, a polycrystalline silicon carbide layer 28 is formed on it (C). An etching operation is executed; after that, a silicon oxide layer 30 is formed; electrodes 32, 34, 36 are formed. Thereby, a transistor is obtained.
Inventors:
UEDA SHIGEYUKI
Application Number:
JP28501991A
Publication Date:
May 25, 1993
Filing Date:
October 30, 1991
Export Citation:
Assignee:
ROHM CO LTD
International Classes:
H01L29/165; H01L21/331; H01L29/73; H01L29/737; (IPC1-7): H01L21/331; H01L29/165; H01L29/73
Attorney, Agent or Firm:
Furuya Eiko