Title:
選択的ページミス変換プリフェッチによってプログラムメモリコントローラにおけるページ変換ミスレイテンシを隠すこと
Document Type and Number:
Japanese Patent JP6718454
Kind Code:
B2
Abstract:
This invention hides the page miss translation latency for program fetches. In this invention whenever an access is requested by CPU, the L1I cache controller does a-priori lookup of whether the virtual address plus the fetch packet count of expected program fetches crosses a page boundary. If the access crosses a page boundary, the L1I cache controller will request a second page translation along with the first page. This pipelines requests to the μTLB without waiting for L1I cache controller to begin processing the second page requests. This becomes a deterministic prefetch of the second page translation request. The translation information for the second page is stored locally in L1I cache controller and used when the access crosses the page boundary.
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Inventors:
Ramakrishnan Venkatas Bramanian
Orlai Oru Road
Bipin Prasad Hellemagalur Rama Prasad
Orlai Oru Road
Bipin Prasad Hellemagalur Rama Prasad
Application Number:
JP2017533975A
Publication Date:
July 08, 2020
Filing Date:
December 22, 2015
Export Citation:
Assignee:
Texas Instruments Japan Ltd.
Texas Instruments Incorporated
Texas Instruments Incorporated
International Classes:
G06F12/1027; G06F9/32; G06F9/38; G06F12/0862; G06F12/1045
Domestic Patent References:
| JP5298185A |
Foreign References:
| US20060248279 | ||||
| WO2007052369A1 | ||||
| US20140115294 |
Attorney, Agent or Firm:
Kyozo Katayose