To increase the number of CPU's which can be connected to a system in the multiprocessor system.

CPU's 10-12 are connected to a bus bridge 30 through a host bus 20 and CPU 13-15 are connected to a bus bridge 32 through a host bus 22. The bus bridges 30 and 32 are connected to a main memory 50 and an I/OF device 52 through a slave bus 40. Bridge caches 31 and 33 shared by host CPU 10-12 and 13-15 are connected to the bus bridges 30 and 32. The host buses 20 and 22 are split buses and CPU's 10-15 can deal with the split. The number of CPU's which can be connected is increased by hierarchization with such constitution, and the deterioration of throughput and latency, accompanying hierarchization, can be prevented by the adoption of the bridge cache and by making the host buses into the split buses.