HIERARCHICAL COLUMN SELECTION LINE ARCHITECTURE FOR MULTI-BANK DRAM - INTERNATIONAL BUSINESS MASCHINES CORPORATION

Title:

HIERARCHICAL COLUMN SELECTION LINE ARCHITECTURE FOR MULTI-BANK DRAM

Document Type and Number:

Japanese Patent JP3229267

Kind Code:

B2

Abstract:

PROBLEM TO BE SOLVED: To provide a multi-bank DRAM having hierarchical column selection line architecture.
SOLUTION: Plural memory cells, which are formed into at least two banks A, B, are provided in a DRAM. Each of banks comprises a memory cell arranged in row and column. The memory cell stores data given by at least one bit line 503 and at least one data line 505. The DRAM is connected to a first switch 507 selecting one bank out of two banks, comprises a second switch 508 selecting one of columns, the first and the second switches 507, 508 couple one of bit lines to one of data lines, and writing data or reading data for a common memory cell for a bank selecting data and a selected column can be performed.

Inventors:

Kirihata Toshiaki

Application Number:

JP23189198A

Publication Date:

November 19, 2001

Filing Date:

August 18, 1998

Export Citation:

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