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Patent Searching and Data


Title:
HIERARCHICAL WIRING METHOD
Document Type and Number:
Japanese Patent JPH0962719
Kind Code:
A
Abstract:

To increase the mount density of a semiconductor integrated circuit that is designed and mounted on a hierarchical basis by performing wiring by using a wiring pattern which is already wired in a low layer, making connections at halfway points of wires in components, and removing wires which become unnecessary.

When there is connection relation among a component D302, a component 304, and a component F306 in a low layer, a circuit element D314, E315, or 316 and a component end point E317, F318, G319, or H320 are wired together by wiring in the components in the low layer. Then, the closest halfway points of wiring patterns in the respective components which are already wired in the low layer are wired together as shown by wiring F308 or wiring G309. Then removal information is added to a wire H310, I311, or J312 which becomes an unnecessary wiring pattern to remove the unnecessary wire while wiring path information is saved.


Inventors:
MUNEMURA TAIZO
NAGASE HACHIDAI
SHIGA AKIO
SUZUKI KATSUKI
Application Number:
JP21700995A
Publication Date:
March 07, 1997
Filing Date:
August 25, 1995
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/82; G06F17/50; (IPC1-7): G06F17/50; H01L21/82
Attorney, Agent or Firm:
Ogawa Katsuo