Title:
階層ワード線方式の半導体記憶装置と、それに使用されるサブワードドライバ回路
Document Type and Number:
Japanese Patent JP4245147
Kind Code:
B2
Abstract:
In a sub word driver circuit in a semiconductor memory device of a hierarchy word structure using a main word line signal and a sub word line signal, a first NMOS transistor and a first PMOS transistor are connected in series. A second NMOS transistor is connected with a node between the first PMOS transistor and the first NMOS transistor. The source of the first PMOS transistor is connected with a sub word line inverted signal obtained by inverting the sub word line signal, and the source of the first NMOS transistor is connected with a first negative voltage. A single main word line signal is connected to a gate of the first PMOS transistor and a gate of the first NMOS transistor, and the sub word line signal is connected with a gate of the second NMOS transistor.
Inventors:
Chiaki Dono
Koji Koshikawa
Koji Koshikawa
Application Number:
JP2003367966A
Publication Date:
March 25, 2009
Filing Date:
October 28, 2003
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
G11C8/08; G11C11/407; G11C8/14; G11C11/401
Domestic Patent References:
| JP2001351379A | ||||
| JP2001297583A | ||||
| JP2002352580A |
Attorney, Agent or Firm:
Minoru Kudo