Title:
SEMICONDUCTOR STORAGE DEVICE
Document Type and Number:
Japanese Patent JP3192344
Kind Code:
B2
Abstract:
PURPOSE: To enable erasing operation having high reliability at high speed almost without increasing the chip size by connecting the output node of a high-voltage generating circuit for a non-volatile semiconductor storage device by a switching circuit.
CONSTITUTION: A signal TRAN is at an 'L' level, transistor switches Qd1, Qd2 are brought to an off-state, and VPP, VMBL and VMWL nodes output different voltage respectively at the time of write operation. The signal TRAN is at an 'H' level, the switches Qd1, Qd2 can transfer 20V, and voltage output from potential boosting circuits 31-32 is short-circuited (output as voltage 20V for erase) at the time of erase operation. Only a 20V limiter 41 is operated in limiters, and all VPP, VMBL and VMWL nodes are kept at 20V. Accordingly, the high-voltage charging time for erase can be shortened, and the efficiency of usage of the circuits is improved.
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Inventors:
Hiroshi Nakamura
Toru Tanzawa
Toru Tanzawa
Application Number:
JP5621895A
Publication Date:
July 23, 2001
Filing Date:
March 15, 1995
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G11C17/00; G11C5/14; G11C16/04; G11C16/06; G11C16/30; H01L21/8247; H01L27/115; (IPC1-7): G11C16/06; H01L21/8247; H01L27/115
Domestic Patent References:
| JP3108195A | ||||
| JP1185461A | ||||
| JP1173500A | ||||
| JP27293A | ||||
| JP61137299A |
Attorney, Agent or Firm:
Takehiko Suzue