Title:
High dielectric-breakdown-voltage LDMOS device
Document Type and Number:
Japanese Patent JP6176838
Kind Code:
B2
Abstract:
A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).
Inventors:
Hong Ning Yang
Daniel Jay Bromberg
Gian-Kai Tsuo
Daniel Jay Bromberg
Gian-Kai Tsuo
Application Number:
JP2013127559A
Publication Date:
August 09, 2017
Filing Date:
June 18, 2013
Export Citation:
Assignee:
NXP USA,Inc.
International Classes:
H01L29/786; H01L21/336; H01L27/088; H01L29/06
Domestic Patent References:
| JP2007158098A | ||||
| JP2000223665A | ||||
| JP2006310770A | ||||
| JP5136436A | ||||
| JP2009088199A |
Attorney, Agent or Firm:
Atsushi Honda
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