Title:
高周波ノイズ対策回路
Document Type and Number:
Japanese Patent JP6451689
Kind Code:
B2
Abstract:
A circuit board with a measure against high frequency noise includes: an interconnect substrate having an interconnect pattern to which an IC which is a source of high frequency noise is electrically connected; a pair of lands provided on a mounting surface of the interconnect substrate; and a chip component having a body composed of a magnetic body (i.e., ferrite) in a rectangular parallelepiped, and a pair of external electrodes provided at opposite ends of the body, the pair of external electrodes being connected to the pair of lands, the body being disposed on the interconnect pattern, as observed in a direction perpendicular to the mounting surface.
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Inventors:
Yu Ishiwatari
Application Number:
JP2016093253A
Publication Date:
January 16, 2019
Filing Date:
May 06, 2016
Export Citation:
Assignee:
MURATA MANUFACTURING CO.,LTD.
International Classes:
H05K9/00; H03H7/01; H04B15/02
Domestic Patent References:
| JP5067896A | ||||
| JP2010171290A | ||||
| JP2003115691A | ||||
| JP2013115053A |
Attorney, Agent or Firm:
Kazuhiro Ueda