To improve operation efficiency over a wide output power range.
Transistors 10, 12 are connected in parallel with each other and amplify high frequency signals inputted from the outside. A switch 18 has an input terminal 18a connected to output of the transistor 10 and output of the transistor 12, an output terminal 18b, and an output terminal 18c. The switch 18 connects the input terminal 18a either to the output terminal 18b or the output terminal 18c. A transistor 20 amplifies a signal outputted from the output terminal 18b. A switch 24 has an input terminal 24a connected to output of the transistor 20, an input terminal 24b connected to the output terminal 18c, and an output terminal 24c. The switch 24 connects either the input terminal 24a or the input terminal 24b to the output terminal 24c. Output power of the transistor 10 is larger than output power of the transistor 12, and operation efficiency of the transistor 10 is lower than operation efficiency of the transistor 12.
| WO/2018/080732 | LOW IMPEDANCE ADAPTIVE BIAS SCHEME FOR POWER AMPLIFIER |
| JP2022532679 | Bias voltage connection in RF power amplifier packaging |
| WO/2017/173119 | MULTI-MODE STACKED AMPLIFIER |
HARUNA TAKAO
TAKAAI JUN
| JPH0936675A | 1997-02-07 | |||
| JP2000209049A | 2000-07-28 | |||
| JPH118560A | 1999-01-12 | |||
| JPH07336168A | 1995-12-22 | |||
| JPH0936675A | 1997-02-07 | |||
| JP2000209049A | 2000-07-28 |
Hideki Takahashi
Yoshimi Kuno
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