Title:
HIGH-FREQUENCY PROGRAMMABLE FREQUENCY DIVIDER
Document Type and Number:
Japanese Patent JP3503967
Kind Code:
B2
Abstract:
PURPOSE: To make a clock frequency highest by constituting a frequency diver, so that the maximum speed of the divider may become closer to those designated to individual counters.
CONSTITUTION: A 16-bit high-speed frequency divider operates to a highest frequency of 650 MHz and divides an arriving clock frequency by an integer N expressed by a binary number. In this case, the frequency divider is provided with 8-bit ECL programmable counters 31 and 32, which have a maximum speeds of at least 700 MHz, and a shift register 33 is constituted of one ECL flip-flop. An ECL clock driver 30 is provided with a plurality of outputs, and one of the outputs is designated to have a very low differential time delay (skew). The driver 30 receives a clock signal 60 through its input, and the output signals 38-40 of the driver 30 are distributed to the clock inputs of the counters 31 and 32 and shift register 33 through the lines 35-37 of a print circuit. The relative arrival time for each signal varies, depending on the propagation delays of the lines 35-37.
Inventors:
Timothy El Hilstrom
Application Number:
JP25797693A
Publication Date:
March 08, 2004
Filing Date:
October 15, 1993
Export Citation:
Assignee:
AGILENT TECHNOLOGIES, INC.
International Classes:
H03K23/40; H03K23/64; H03K23/66; (IPC1-7): H03K23/64; H03K23/40
Domestic Patent References:
| JP3106223A | ||||
| JP461420A | ||||
| JP61251325A | ||||
| JP61176213A |
Attorney, Agent or Firm:
Kaoru Furuya (2 outside)