Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
HIGH LOAD STATUS EVALUATING CIRCUIT FOR INPUT/OUTPUT CONTROL DEVICE
Document Type and Number:
Japanese Patent JPH05181763
Kind Code:
A
Abstract:

PURPOSE: To reduce work, time and cost required for connecting channels and respective devices by generating a high load state without connecting a peripheral control device and a peripheral device to plural channels.

CONSTITUTION: An I/O control device is provided with a data transfer control part 10 for controlling data transfer between plural channel control parts 30 and a master device (main storage), a processor 20 for controlling the control part 10, a control storage part 40 storing firmware for driving the processor 20, a counter 50 for setting up the time interval of execution suppression, a subtractor 60 for subtracting the counter 50, and an execution suppressing circuit 70 for generating an execution suppressing signal to the processor 20 when the value of the subtractor 60 is turned to '0'.


Inventors:
TSUKAHARA KATSUMI
Application Number:
JP36012591A
Publication Date:
July 23, 1993
Filing Date:
December 27, 1991
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC IBARAKI LTD
International Classes:
G06F13/00; G06F13/12; (IPC1-7): G06F13/00; G06F13/12
Attorney, Agent or Firm:
Murao Mikio