Title:
HIGH-PERFORMANCE DIGITAL IC PACKAGE USING BGA-TYPE I/O FORMAT AND SINGLE-LAYER CERAMIC PLATE BOARD BY BIMETAL FILLING VIA
Document Type and Number:
Japanese Patent JPH09213829
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To enable strict control of coplanarity and enable a number of connections in a small unit area without increasing the number of layers, by using a pole grid array format and a single-layer ceramic plate board having a number of vias which are filled with bimetal and precisely positioned. SOLUTION: On a single-layer board having predetermined patterns of vias 22, 25, a plurality of circuit tracers extending from a plurality of wire bonding pads 19 or flip-flop mounting pads are provided for the plurality of vias 22, 25 in order to cause electric contact with each other. A protector 32 protects the vias 22, 25, the tracers, the wiring bonding pads 19, wire bonds 20 and a die 30 from the environment. On a surface opposite to the board surface where the die 30 is provided, a plurality of conductive balls 17 are provided. Thus, strict control of coplanarity is enabled without increasing the number of layers.
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Inventors:
NOOMAN ERU GURIINMAN
EMU PII RAMACHIYANDORA PANITSU
JIYOOJI EMU HERUNANDEZU
EMU PII RAMACHIYANDORA PANITSU
JIYOOJI EMU HERUNANDEZU
Application Number:
JP14321096A
Publication Date:
August 15, 1997
Filing Date:
June 05, 1996
Export Citation:
Assignee:
CIRCUIT COMPONENTS INC
International Classes:
H01L23/12; H01L23/055; H01L23/31; H01L23/367; H01L23/498; (IPC1-7): H01L23/12
Attorney, Agent or Firm:
Hironori Takenori
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