Title:
HIGH RESISTANCE LOAD TYPE SRAM INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH06168593
Kind Code:
A
Abstract:
PURPOSE: To detect the decrement of a high resistance constituting a high resistance load type memory cell and a junction leakage defect without injuring a function as a memory integrated circuit.
CONSTITUTION: High resistors HR1 and HR2 constituting the high resistance load type memory cell 10 are made switchable to a state connected to power source, a state connected to ground and a state connected to any of no power source and no ground. Then, bit lines B, B- are made separatable from precharging lines 3, 4, and the value of currents flow through the bit lines B, B- are made measurable individually by current detection type amplifiers 13, 14.
Inventors:
SHIBATA KEIJI
Application Number:
JP32088092A
Publication Date:
June 14, 1994
Filing Date:
November 30, 1992
Export Citation:
Assignee:
KAWASAKI STEEL CO
International Classes:
G11C11/413; G11C29/00; G11C29/04; H01L21/8244; H01L27/11; (IPC1-7): G11C11/413; G11C29/00; H01L27/11
Attorney, Agent or Firm:
Tetsuya Mori (2 others)