Title:
HIGH-SPEED ADDRESS COMPARATOR CIRCUIT FOR MEMORY PROVIDED WITH REDUNDANT ADDRESS SPECIFIED CONSTITUTING MEMBER
Document Type and Number:
Japanese Patent JP2638357
Kind Code:
B2
Abstract:
PURPOSE: To simplify circuit constitution by providing two elements for respective bit positions and performing constitution by two serially connected FETs inside the respective elements.
CONSTITUTION: Representative elements T10 and T11 are constituted of the two FETs for receiving an address bit A0 and a complement address bit F0B, the other representative elements T12 and T13 are constituted of the FETs for receiving the complement address bit A0B and the address bit F0 and input is inputted to the gate of the FET. When all the address bits A0-A9 match, all the FETs are turned OFF, nodes N1 and N2 are separated, the capacitance of the node N1 is connected to a Vcc by a latch circuit 12, the node N2 is grounded by the latch circuit 14 and a high level is outputted. When a non- matching address bit is present, one of the elements is conducted, the two nodes are turned to the same level and a low level is outputted through an inverter 16. Thus, this comparator circuit 15 simplified.
Inventors:
ROBAATO ESU MAO
Application Number:
JP28871591A
Publication Date:
August 06, 1997
Filing Date:
November 05, 1991
Export Citation:
Assignee:
ETORON TEKUNOROJII INC
International Classes:
G11C11/413; G11C29/00; G11C29/04; G11C29/12; (IPC1-7): G11C29/00; G11C11/413
Domestic Patent References:
| JP6337899A | ||||
| JP5611338B2 |
Attorney, Agent or Firm:
Kyozo Yuasa (6 people outside)
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