Title:
高速クロックイネーブルラッチ回路
Document Type and Number:
Japanese Patent JP3559712
Kind Code:
B2
Abstract:
A novel latch circuit configuration (100) that substantially reduces inverter-based setup and hold times includes first and second input switches (140, 145) connected to an effective sense amplifier configuration. It is possible for the input switches to receive complimentary signals of a balanced input signal. The latch circuit operates in initialization and output modes based on the signal level of an alternating clock signal. The output mode produces an output signal having a first or second signal magnitude based on the magnitude of the input signal at the end of the initialization mode. Also, disclosed is a high-speed serial-to-parallel converter based on this latch circuit.
Inventors:
The Deus John Gabara
Application Number:
JP22262798A
Publication Date:
September 02, 2004
Filing Date:
August 06, 1998
Export Citation:
Assignee:
Lucent Technologies, Inc.
International Classes:
H03K3/356; H03M9/00; (IPC1-7): H03K3/356
Domestic Patent References:
| JP5175803A | ||||
| JP5129904A | ||||
| JP5175803A | ||||
| JP5129904A |
Attorney, Agent or Firm:
Masao Okabe
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa