Title:
HIGH-SPEED COUNTER CIRCUIT
Document Type and Number:
Japanese Patent JP3309361
Kind Code:
B2
Abstract:
PURPOSE: To enable the designing of an efficient high-speed counter structure used for measuring an arbitrary range.
CONSTITUTION: The high-speed counter is a functional block structure flexibly connected by a bus structure. A set of independent counter blocks 82 are connected to a programmable comparator block 104 having a prescribed count threshold by the bus structure. The outputs of two pieces of the comparators 104 are connected to a switchable AND/OR block 110 and indicate a range. The functions are divided to the block and the connecting bus structure, by which the respective rest counter structures are efficiently programmed so as to meet the momentary application.
Inventors:
Gary Parker
Application Number:
JP7156192A
Publication Date:
July 29, 2002
Filing Date:
March 27, 1992
Export Citation:
Assignee:
Allen-Bradley Company, Inc.
International Classes:
G05B19/05; G05B19/042; G05B19/18; H03K21/00; H03K23/00; (IPC1-7): G05B19/05; G05B19/18; H03K23/00
Domestic Patent References:
| JP5715046A |
Other References:
【文献】米国特許3824378(US,A)
Attorney, Agent or Firm:
Akira Asamura (3 outside)