PURPOSE: To obtain a high-speed processing circuit without using a high-speed output buffer by analyzing the data on a high-speed reading clock with a low- speed reading clock and then multiplexing said data in the same sequence as the analyzing mode.

CONSTITUTION: A reading clock 105 is divided into two pieces of low-speed reading clocks 117/118 and 119/120 by dividers 109 and 116 respectively. In this case, the clocks 118 and 120 are supplied to a synchronizing circuit 112 to secure synchronization between the dividers 109 and 116. These internal low-speed clocks 117 and 118 have phases opposite to each other, and therefore a signal 101 is decomposed to data streams 121 and 122 by flip-flops 107 and 108. Clocks 117 and 118 have double cycles compared with the clock 105 and therefore the phase matching is possible between these two clocks when data 121 and 123 pass through output buffers 110 and 111. These data are multiplexed by a double multiplexing circuit 115 and set in the same array as the data on the original signal 101.