Title:
高速動的周波数分周器
Document Type and Number:
Japanese Patent JP4856458
Kind Code:
B2
Abstract:
The frequency divider includes the buffer 30, the function selector 31 and the inverter 32. The output of the function selector 31 is input to the buffer 30. The output of the buffer 30 is fed back to the function selector 31 by two paths. One path includes the inverter 32 and the other does not. The function selector 31 selects one of the paths in synchronous with input clock CK. At one timing the output of the buffer 30 is flipped by the inverter 32. At the next timing the output of the buffer 30 is held the same by the function selector 31 selecting the path not including the inverter 32.
Inventors:
Makoto Hariko
Application Number:
JP2006089544A
Publication Date:
January 18, 2012
Filing Date:
March 28, 2006
Export Citation:
Assignee:
富士通株式会社
International Classes:
H03K23/44
Domestic Patent References:
| JP60224319A | ||||
| JP3126314A | ||||
| JP595281A | ||||
| JP5102312A | ||||
| JP200243928A |
Attorney, Agent or Firm:
Yoshiyuki Osuga
Motoaki Hisagi
Motoaki Hisagi