HIGH SPEED INCOMING SELECTOR FOR BUS ORIENTATION COMPUTER SYSTEM

Japanese Patent JPS5263638

A

1518565 Data processing system NCR CORP 4 Nov 1976 [19 Nov 1975] 45915/76 Heading G4A [Also in Division H4] In a data processing system including a plurality of units such as processors, stores, I/O devices &c., each connected to a common data bus 12 via a respective adaptor (only one shown), a unit 11 wishing to transmit data to another unit sends a request 174, the data 156, and the destination address 158 to its adapter. The destination address is decoded at 16 whereupon unit 17 examines the state of a busy line 97 associated with the destination unit adapter, all busy lines being connected to each adapter via lines 18. If the destination adapter busy line shows "not busy" gate 20 is enabled via line 178 and an access request 176 is applied to the bus 12. The unit 17 also applies a "busy" signal to the busy line in the destination adapter. A priority unit selects the highest priority requesting unit and supplies a signal 190 to set a request granted flip-flop 15 in the relevant adapter. Flip-flop 15 enables gates 14 to gate the data and destination address on to the bus. The busy signal 97 in the destination adapter sets flip-flops 21, 96 to enable gates 23 to connect the adapter to bus to receive the data. Error checks are performed both on the bus, a parity check, and in the receiving unit, an error setting status logic 24 to cause the transmission to be repeated.

JIYATSUKU RONARUDO DEYUUKU
FUIRITSUPU UESUREI BURUTSUKUSU
ROBAATO RONARUDO ERUZAA

JP13695276A

May 26, 1977

November 16, 1976

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NCR CO

G06F13/36; G06F13/364; (IPC1-7): G06F3/00

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