Title:
HIGH-SPEED JUDGMENT CIRCUIT FOR SHORT-CIRCUIT FAILURE
Document Type and Number:
Japanese Patent JP3207643
Kind Code:
B2
Abstract:
PURPOSE: To prevent a malfunction of a momentary level change caused by noises or serge voltages, by comparing a previously set value with a difference between an output of a first integration circuit, in which an output from a half-wave rectification circuit is entered, and an output from an adder after an output of a second integration circuit and an output of a level detection circuit, in which an output of a delay circuit is entered, are added by the adder.
CONSTITUTION: Half-wave rectification circuits 3 and 4 rectify each half wave of a detection current in proportion to a load current. Each output of the half-wave rectification circuits 3 and 4 is entered into first integration circuits 9 and 11 and delay circuits 5 and 6. The output of the delay circuits 5 and 6 is entered into level detection circuits 13 and 14 and second integration circuits 10 and 12. After that, each output of the level detection circuits 13 and 14 and each output of the second integration circuits 10 and 12 are added by addition circuits 13 and 14. Then, subtraction circuits 17 and 18 calculate a difference between the output of the addition circuits 15 and 16 and the output of the first integration circuits 9 and 11. Each output of the subtraction circuits 15 and 16 is compared with a previously set value by comparison circuits 20 and 21. Consequently, 3 malfunction caused by noises and serge voltages can be prevented.
Inventors:
Seiichi Nakamura
Application Number:
JP30074293A
Publication Date:
September 10, 2001
Filing Date:
December 01, 1993
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G01R31/02; H02H3/08; H02H3/093; H02H3/50; (IPC1-7): H02H3/093; G01R31/02; H02H3/08; H02H3/50
Domestic Patent References:
| JP50106153A | ||||
| JP6281925A | ||||
| JP3159517A |
Attorney, Agent or Firm:
Hidekazu Miyoshi