To provide a high speed locking circuit for recovering a reference signal such as a clock signal and a carrier by using a tuning circuit whose Q is high and whose time constant is constant under a burst communication environment.
A switch 20 is provided to an input part of a tuning circuit 18 and a series circuit consisting of a delay circuit 23, a phase shifter 22 and an amplifier 21 receiving an output of the tuning circuit 18 is provided. At a start point of a guard time of a time division multiple access(TDMA) signal, a switch 20 is thrown to provide an output of a clock recovery circuit 17 or an inverse modulation circuit 25 to an input to the tuning circuit 18 and an output from the series circuit (21, 22, 23) to the input to the tuning circuit 18. In the series circuit (21, 22, 23), the signal is processed nearly to be equal- amplitude inverse-phase so as to reduce a burst resident in a guard time thereby decreasing interference between bursts.
WATANABE KAZUJI
UMEHIRA MASAHIRO
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