HIGH-SPEED COUNTER/DIVIDER AND METHOD FOR USING SAID COUNTER/DIVIDER AS SWALLOWER COUNTER

Title:

HIGH-SPEED COUNTER/DIVIDER AND METHOD FOR USING SAID COUNTER/DIVIDER AS SWALLOWER COUNTER

Document Type and Number:

Japanese Patent JPH04258023

Kind Code:

A

Abstract:

PURPOSE: To obtain a counter for counting an input pulse, and for easily supplying the integral squares of 2 or the integral squares of 2 the half of a counted pulse at the time of each output pulse. CONSTITUTION: A counter/divider for dividing an input frequency F1 by 2 +1/2 comprises a first divider 30 by 2 which receives a signal for dividing a frequency F1, and supplies a 2 output with a frequency F1/2 with phase shift from the former to latter of 360 deg./2 , multiplexer 32 having a control terminal 34 which continuously supplies a 2 output as an output 33 in each time obtained from a control signal supplied to this control terminal, and second divider 31 by 2 which receives the output of the multiplexer output 33, and supplies the desired output 34 of the counter/divider to be supplied to the control terminal of the multiplexer.

Inventors:

JIYANNRUTSUKU JIYAFUAARU
ROIKU RIITAA
MITSUSHIERU MUURE

Application Number:

JP26056291A

Publication Date:

September 14, 1992

Filing Date:

September 12, 1991

Export Citation:

Click for automatic bibliography generation Help

Assignee:

SGS THOMSON MICROELECTRONICS

International Classes:

H03K23/64; G06F1/025; H03K23/68; (IPC1-7): H03K23/64

Attorney, Agent or Firm:

Keiichi Yamamoto

Previous Patent: 超音波トランスジューサおよびそれを用いた超音波治療装置

Next Patent: ゼロテーパスタック