PURPOSE: To provide a high-speed pattern generator wherein the generation of a test pattern is made high-speed.

CONSTITUTION: A plurality of buffer memories 611 to 614 are provided at the rear stage of a pattern generator 2. An output pattern 610 of the pattern generator 2 is input to each input end. A control circuit 641 for controlling an address signal and a writing/reading signal of each buffer memory 611 to 614 provided. A counter 642 for counting a pattern number is provided. A multiplexer 62 for multiplexing and taking out each output of the buffer memories 611 to 614 is provided. In addition, a plurality of banks are provided in accordance with the above constitution and another multiplexer for selecting each output is set. A bank control circuit is provided. As the result, the high-speed pattern generator is constituted.