To enable counting of a high-speed pulse highly stably without any error.

A latch/request signal periodically issued from a pulse counter 2 side is transmitted through a cable 15 to a latch 5 as a latch signal. The latch 5 latches the count value of a counter 4 each time the latch receives the latch signal, the latched count value is serially transmitted via a serial transmission I/F 6 and the cable 15 to a pulse counter 2, and then stored in a memory 13. The pulse counter 2 can periodically acquire the count value data. Thus, even when abnormal transmission took place and this caused an error in the count value data acquired on the pulse counter 2 side, next-time count value data enables recovery from the error. Since the pulse to be measured is not transmitted directly onto the cable 15, the device will be substantially not influenced by external noise.