Title:
HIGH-SPEED READING CIRCUIT FOR SEGMENT DATA
Document Type and Number:
Japanese Patent JPS6393078
Kind Code:
A
Abstract:
PURPOSE:To perform write and read operations in parallel with each other and to increase the data transfer speed by using a 2-port memory to a segment memory and at the same time using a segment memory and a serial access memory which controls a memory control circuit. CONSTITUTION:The data on a CPU bus 7 and a graphic-only bus 8 are supplied to and delivered from a segment memory 12 having a 2-port memory structure via an input/output buffer 14. The address of the buffer 14 is supplied to the memory 12 and a memory control circuit 16 respectively. While the address of the bus 8 is supplied to a serial access memory control part 17. The part 17 controls the working of the circuit 16 and at the same time delivers a read signal to the memory 12. The circuit 16 controls the working of the memory 12 by the address of the bus 7 and the signal of the part 17 and performs the write/read operations with the bus 7 and the data reading operation to the bus 8 in parallel with each other. Thus the data transfer speed is increased.
Inventors:
KURAMATA YOSHIMITSU
Application Number:
JP23828186A
Publication Date:
April 23, 1988
Filing Date:
October 07, 1986
Export Citation:
Assignee:
SEIKO INSTR & ELECTRONICS
International Classes:
G06F12/00; G06F13/18; G06T1/60; (IPC1-7): G06F12/00; G06F15/64
Attorney, Agent or Firm:
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