PURPOSE: To transmit the long data of 256 bits once and to improve an efficiency of a CPU by replacing a serial transmitting LSI by a DRAM equipped with a shift register.

CONSTITUTION: A synchronization of a shift output is taken by an inversion of a shift clock by a flip-flop 5 and the shift output passes through a driver receiver 6. In a remote side, the bit data is usually shifted in a shift register 8 by the shift clock and when the data coincides with a pattern of 8 bits, an SIE signal is set. When the SIE signal is set, a RAM B 4 shifts in the data to an internal shift register 60. If the SIE signal is reset when the pattern of the 8 bits appears again, the reception of the data of just 256 bits is completed. Thereby, the efficiency in transmission is improved.