PURPOSE: To enable high-speed synchronous data transfer which is not affected by signal transmission delay time on a printed circuit board between a master device 1 and slave devices 2.

CONSTITUTION: The master device 1 is provided at one end of parallel bus lines and the slave devices 2-1 to 2-3 are provided on the bus lines; and two lines which are a signal line 31 for sending a clock 2 signal by the toaster device 1 and a signal line 32 for receiving it are provided and those two signal lines are coupled at the end on the opposite side from the master device 1, so that the clock signal sent by the signal line 31 is sent back to the side of the signal line 32. Then the master device 1 sends a data transfer request REQ to the slave devices 2 by using the transmission-side clock signal. The slave devices 2 sends a data signal Data to the master device 1 together with a response signal ACK by using the reception side clock signal. The master device 1 latches the data signal by using the reception-side clock signal. In this case, the clock signal which is sent first is sent back to the master device 1 and return data latching is enabled together with the data signal, so the transmission clock period can be increased.