Title:
HIERARCHICAL LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3130880
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To simply perform a logical design and a layout design including also the verification of the designs.
SOLUTION: The layout design method of a semiconductor integrated circuit comprises a step for performing an automatic layout connection wirings so that the wiring paths between blocks become short after a step for arranging these blocks on a high-order hierarchy; a step wherein terminals are formed on the boundaries between passage blocks in the passage wiring paths on the blocks, on which the wirings pass through, that is, the above passage blocks, and the passage wiring paths of these blocks are buried in the blocks after the above automatic layout step; a hierarchy formation step for forming blocks adaptable to a new macro cell, wherein layers having the above terminals and buried wirings are formed into the high-order hierarchy, and the passage blocks are formed into a low-order hierarchy; and a step for performing a hierarchical expansion processing of the new macro cell at the uppermost layer.
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Inventors:
Yukio Minoda
Application Number:
JP32931598A
Publication Date:
January 31, 2001
Filing Date:
November 19, 1998
Export Citation:
Assignee:
NEC IC Microcomputer System Co., Ltd.
International Classes:
H01L21/822; G06F17/50; H01L21/82; H01L27/04; (IPC1-7): H01L21/82; G06F17/50; H01L21/822; H01L27/04
Domestic Patent References:
| JP4333260A | ||||
| JP243755A | ||||
| JP4741A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)