PURPOSE: To designate the complicated trace conditions in addition to the detailed trace conditions by providing a trace condition memory, etc., as well as a trace condition register and a trace counter register.

CONSTITUTION: A trace condition memory 20 holds the data fetched by a trace counter register 16 and then sets these data to a trace condition register 15 and the register 16 at a time point when the output of a decrementer 17 is equal to 0. While the read address of the memory 20 is designated by a trace condition memory control circuit 21. The address of the memory 20 is replaced when the decrementer 17 detects 'all-0'. In such a way, both detailed and complicated trace conditions can be designated with use of the memory 20 and the circuit 21 as well as both registers 15 and 16 which perform tracing actions in response to their internal states.